This call (H2020-JTI-EuroHPC-2020-02) was announced in the annual Work Plan of the EuroHPC JU for the year 2020 and is a follow-up of the Specific Grant Agreement (EPI-SGA1: 826647), which established the European Processor Initiative (EPI) in 2018.
The EPI is facilitating the development of exascale supercomputers, computing systems able to perform more than one trillion (1018) operations per second. The EPI aims at providing industry in Europe with a competitive edge in processor technology to be further exploited across a wide range of applications from engineering, science and bio-medical to automotive, manufacturing, finance and emerging big-data and smart objects fields.
Deadline for proposals
12. Jauary 2021
Experts in IT
In particular, the proposal will build on the results of the Phase 1 of the European Processor Initiative (EPI), and is expected to cover the following topics:
- Development of the second generation of low-power general purpose processing system units. Generate the functional and non-functional requirements (using representative HPC and big-data benchmarks, emerging applications specifications (in the automotive sector for example), and targeting maximum energy-efficiency and reliability; design the architecture of the processing system units; verify, tape-out, validate, test and bring up the processing system units; develop the required firmware and system software leveraging, as much as possible, on open source efforts and solutions.
- Development of the second generation of low-power processing system units for application acceleration. Generate their functional and non-functional requirements (using relevant representative HPC and big data benchmarks and emerging applications) and design their architecture to accelerate specific HPC and big data applications, including as edge and embedded automotive applications or other emerging applications. The applications must have high-volume potential. Processing units will be realised as standalone components, distributed collaborating systems or IP-blocks, and will include stand-alone open RISC V hardware approaches for accelerators with connectivity not limited to the EPI processing units, addressing a large number of application areas. Work in this topic is required to interface with topic a) in order to achieve maximum interoperability (including IP-block interfacing) and roadmap synchronisation.
- Validation of the first generation of low-power processing system units developed in Phase 1 (and Phase 2). Finalize the required firmware and system software leveraging, as much as possible, on open source efforts and solutions; development and integration of the boards/blades and test benches to demonstrate the processing units and accelerators developed in Phase 1 (and Phase 2) of EPI with the porting of representative sets of real-life kernels for the chosen application(s). This will address also the integration and interconnection of the EPI hardware ecosystem with other approaches.
- Support for a hardware and software development platform common to different processor and accelerator types. This platform should be accessible by a wide range of interested parties. Support should also be directed towards maximising early on the uptake by users of processor and accelerator technology developed in Phases 1 and 2 of EPI for testing purposes.
Total budget: EUR 35 million
Head of Unit
High Performance Computing and Quantum Technology (Unit C.2)
Phone: +352-4301 32866